Integrated semiconductor memories, such as Dynamic Random Access Memories (DRAMs), have a multiplicity of memory cells that are arranged in a memory cell array and that are connected to word lines and bit lines. The bit lines are connected to the memory cells to read and write data. In the case of a DRAM, the memory cells each typically have a storage capacitor and a selection transistor. Information items stored in the storage capacitors of the memory cells are read out by activation of the word lines and bit lines. The electrical potential of two bit lines is detected by a sense amplifier in order to identify a storage state.
Since many cells in a DRAM are connected in parallel to the same line, considerable amount of energy and time is needed to bring the signal reliably to each corner of the array. One of the biggest factors influencing the signal is the bit line to bit line (BL-BL) capacitance. Such parasitic effects are conventionally compensated for by higher operating voltages and correspondingly higher quantities of charge. However, this increases the current consumption, the heat supply and the space requirement of the integrated semiconductor circuit per memory cell. Other solutions are also used to decrease BL-BL capacitance, such as the use of high-k dielectric materials between bit lines, the use of a dummy bit line between two active bit lines, and the use of larger bit line spacing. Disadvantages of these solutions include increased cost and the need for more horizontal space on the chip, thus resulting in larger chip size. The impetus for higher density devices has made the elimination of cross-talk or cross-coupling between bit lines an even more challenging task.